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isplsi 2096ve 3.3v in-system programmable superfast high density pld 2096ve_08 1 features superfast high density programmable logic 4000 pld gates 96 i/o pins, six dedicated inputs 96 registers high speed global interconnect wide input gating for fast counters, state machines, address decoders, etc. small logic block size for random logic 100% functional, jedec and pinout compatible with isplsi 2096v devices pinout compatible with isplsi 2192ve 3.3v low voltage 2096 architecture interfaces with standard 5v ttl devices high performance e 2 cmos technology f max = 250mhz maximum operating frequency t pd = 4.0ns propagation delay electrically erasable and reprogrammable non-volatile 100% tested at time of manufacture unused product term shutdown saves power in-system programmable 3.3v in-system programmability (isp) using boundary scan test access port (tap) open-drain output option for flexible bus interface capability, allowing easy implementation of wired-or or bus arbitration logic increased manufacturing yields, reduced time-to- market and improved product quality reprogram soldered devices for faster prototyping 100% ieee 1149.1 boundary scan testable the ease of use and fast system speed of plds with the density and flexibility of fpgas enhanced pin locking capability three dedicated clock input pins synchronous and asynchronous clocks programmable output slew rate control flexible pin placement optimized global routing pool provides global interconnectivity lead-free package options description the isplsi 2096ve is a high density programmable logic device containing 96 registers, six dedicated input pins, three dedicated clock input pins, two dedi- cated global oe input pins and a global routing pool (grp). the grp provides complete interconnectivity between all of these elements. the isplsi 2096ve features in-system programmability through the bound- ary scan test access port (tap) and is 100% ieee 1149.1 boundary scan testable. the isplsi 2096ve offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable sys- tems. the basic unit of logic on the isplsi 2096ve device is the generic logic block (glb). the glbs are labeled a0, a1 .. c7 (see figure 1). there are a total of 24 glbs in the isplsi 2096ve device. each glb is made up of four macrocells. each glb has 18 inputs, a programmable and/or/exclusive or array, and four outputs which can be configured to be either combinatorial or registered. inputs to the glb come from the grp and dedicated inputs. all of the glb outputs are brought back into the grp so that they can be connected to the inputs of any glb on the device. the devices also have 96 i/o cells, each of which is directly connected to an i/o pin. each i/o cell can be individually programmed to be a combinatorial input, output or bi-directional i/o pin with 3-state control. the signal levels are ttl compatible voltages and the output drivers can source 4 ma or sink 8 ma. each output can global routing pool (grp) output routing pool (orp) output routing pool (orp) 0919/2096ve c7 c4 c5 c 6 a4 a7 a6 a5 glb logic array dq dq dq dq output routing pool (orp) output routing pool (orp) c3 c0 c1 c2 b0 b3 b2 b1 output routing pool (orp) output routing pool (orp) b7 b6 b4 b5 a0 a1 a3 a2 copyright ? 2004 lattice semiconductor corp. all brand or product names are trademarks or registered trademarks of their respec tive holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. august 2004 t el. (503) 268-8000; 1-800-lattice; fax (503) 268-8556; http://www.latticesemi.com functional block diagram lead- free packag e options av ailable!
specifications isplsi 2096ve 2 be programmed independently for fast or slow output slew rate to minimize overall output switching noise. device pins can be safely driven to 5v signal levels to support mixed-voltage systems. eight glbs, 32 i/o cells, two dedicated inputs and two orps are connected together to make a megablock (see figure 1). the outputs of the eight glbs are connected to a set of 32 universal i/o cells by the two orps. each isplsi 2096ve device contains three megablocks. the grp has as its inputs, the outputs from all of the glbs and all of the inputs from the bi-directional i/o cells. all of these signals are made available to the inputs of the glbs. delays through the grp have been equalized to minimize timing skew. clocks in the isplsi 2096ve device are selected using the dedicated clock pins. three dedicated clock pins (y0, y1, y2) or an asynchronous clock can be selected on a glb basis. the asynchronous or product term clock can be generated in any glb for its own clock. a0 a3 a1 a2 b7 b4 b6 b5 output routing pool (orp) output routing pool (orp) input bus input bus global routing pool (grp) clk 0 clk 1 clk 2 i/o 95 i/o 94 i/o 93 i/o 92 i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 i/o 32 i/o 33 i/o 34 i/o 35 tdo/in 2 tck/in 3 i/o 36 i/o 37 i/o 38 i/o 39 i/o 40 i/o 41 i/o 42 i/o 43 i/o 44 i/o 45 i/o 46 i/o 47 y0 y1 y2 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 63 i/o 62 i/o 61 i/o 60 i/o 59 i/o 58 i/o 57 i/o 56 i/o 55 i/o 54 i/o 53 i/o 52 i/o 51 i/o 50 i/o 49 i/o 48 tdi/in 0 tms/in 1 reset bscan goe 1 goe 0 i/o 91 i/o 90 i/o 89 i/o 88 i/o 87 i/o 86 i/o 85 i/o 84 i/o 83 i/o 82 i/o 81 i/o 80 input bus 0917/2096ve m egablock c7 c6 c5 c4 a4 a5 a6 a7 output routing pool (orp) output routing pool (orp) input bus input bus b0 b1 b2 b3 output routing pool (orp) c3 c2 c1 c0 output routing pool (orp) input bus i/o 79 i/o 78 i/o 77 i/o 76 i/o 75 i/o 74 i/o 73 i/o 72 i/o 71 i/o 70 i/o 69 i/o 68 i/o 67 i/o 66 i/o 65 i/o 64 in 5 in 4 g eneric logic blocks (glbs) functional block diagram figure 1. isplsi 2096ve functional block diagram programmable open-drain outputs in addition to the standard output configuration, the outputs of the isplsi 2096ve are individually program- mable, either as a standard totem-pole output or an open-drain output. the totem-pole output drives the specified voh and vol levels, whereas the open-drain output drives only the specified vol. the voh level on the open-drain output depends on the external loading and pull-up. this output configuration is controlled by a pro- grammable fuse. the default configuration when the device is in bulk erased state is totem-pole configuration. the open-drain/totem-pole option is selectable through the isplever software tools.
specifications isplsi 2096ve 3 absolute maximum ratings 1 supply voltage v cc .................................. -0.5 to +5.4v input voltage applied ............................... -0.5 to +5.6v off-state output voltage applied ............ -0.5 to +5.6v storage temperature ................................ -65 to 150 c case temp. with power applied .............. -55 to 125 c max. junction temp. (t j ) with power applied ... 150 c 1. stresses above those listed under the ?bsolute maximum ratings?may cause permanent damage to the device. functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications). table 2-0008/2096ve parameter minimum maximum units erase/reprogram cycles 10000 cycles c symbol table 2-0006/2096ve c parameter i/o capacitance 6 units typical test conditions 1 2 8 dedicated input capacitance pf pf v = 3.3v, v = 0.0v v = 3.3v, v = 0.0v cc cc i/o in c clock and global output enable capacitance 10 3 pf v = 3.3v, v = 0.0v cc y t a = 0 c to + 70 c t a = -40 c to + 85 c symbol table 2-0005/2096ve v cc v ih v il parameter supply voltage input high voltage input low voltage min. max. units 3.0 3.0 2.0 v ?0.5 3.6 3.6 5.25 0.8 v v v v ss commercial industrial dc recommended operating condition capacitance (t a =25 c, f=1.0 mhz) erase reprogram specifications
specifications isplsi 2096ve 4 input pulse levels table 2-0003/2096ve input rise and fall time input timing reference levels output timing reference levels output load gnd to 3.0v 1.5ns 10% to 90% 1.5v 1.5v see figure 2 3-state levels are measured 0.5v from steady-state active level. test condition r1 r2 cl a 316 ? 348 ? 35pf b 348 ? 35pf 316 ? 348 ? 35pf active high active low c 316 ? 348 ? 5pf 348 ? 5pf active low to z at v +0.5v ol active high to z at v -0.5v oh table 2-0004/2096ve v ol symbol 1. one output at a time for a maximum duration of one second. v = 0.5v was selected to avoid test problems by tester ground degradation. characterized but not 100% tested. 2. measured using six 16-bit counters. 3. typical values are at v = 3.3v and t = 25 c. 4. maximum i varies widely with specific device configuration and operating frequency. refer to the power consumption section of this data sheet and thermal management section of the lattice semiconductor data book or cd-rom to estimate maximum i . table 2-0007a/2096ve 1 v oh i ih i il i il-isp parameter i il-pu i os 2, 4 i cc output low voltage output high voltage input or i/o high leakage current input or i/o low leakage current bscan input low leakage current i/o active pull-up current output short circuit current operating power supply current i = 8 ma i = -4 ma 0v v v (max.) 0v v v 0v v v v = 3.3v, v = 0.5v v = 0.0v, v = 3.0v f = 1 mhz ol oh in il in il in il cc out clock il ih condition min. typ. max. units 3 2.4 125 0.4 10 10 -10 -150 -150 -100 v v a a a a a ma ma cc a out cc cc (v ?0.2)v v v v v 5.25v in cc cc in cc + 3.3v r 1 r 2 c l * device output test point * c l includes test fixture and probe capacitance. 0213a/2096ve figure 2. test load switching test conditions output load conditions (see figure 2) dc electrical characteristics over recommended operating conditions
specifications isplsi 2096ve 5 use isplsi 2096ve-250 for new designs external timing parameters over recommended operating conditions t pd1 units test cond. 1. unless noted otherwise, all parameters use a grp load of four, 20 ptxor path, orp and y0 clock. 2. standard 16-bit counter using grp feedback. 3. reference switching test conditions section. table 2-0030a/2096ve v.1.0 1 3 2 1 tsu2 + tco1 ( ) description # parameter a1 data propagation delay, 4pt bypass, orp bypass ns t pd2 a2 data propagation delay ns f max a3 clock frequency with internal feedback mhz f max (ext.) ? clock frequency with external feedback mhz f max (tog.) ? clock frequency, max. toggle mhz t su1 ? glb reg. setup time before clock, 4 pt bypass ns t co1 a7 glb reg. clock to output delay, orp bypass ns t h1 ? glb reg. hold time after clock, 4 pt bypass ns t su2 ? glb reg. setup time before clock ns t co2 a1 0 glb reg. clock to output delay ns t h2 ? 1 glb reg. hold time after clock ns t r1 a1 2 ext. reset pin to output delay, orp bypass ns t rw1 ? 3 ext. reset pulse duration ns t ptoeen b1 4 input to output enable ns t ptoedis c1 5 input to output disable ns t goeen b1 6g lobal oe output enable ns t goedis c1 7g lobal oe output disable ns t wh ? 8 external synchronous clock pulse duration, high ns t wl ? 9 external synchronous clock pulse duration, low ns -250 min. max. ?.0 250 0.0 3.3 0.0 3.5 1.8 1.8 158 277 2.5 3.0 3.7 6.0 6.0 6.0 4.0 4.0 6.0 -200 min. max. 4.5 200 0.0 4.0 0.0 4.0 2.5 2.5 133 200 3.0 3.5 4.5 6.0 8.0 8.0 5.0 5.0 7.0
specifications isplsi 2096ve 6 external timing parameters over recommended operating conditions t pd1 units -135 min. test cond. 1. unless noted otherwise, all parameters use a grp load of four, 20 ptxor path, orp and y0 clock. 2. standard 16-bit counter using grp feedback. 3. reference switching test conditions section. table 2-0030b/2096ve v.1.0 1 3 2 1 tsu2 + tco1 ( ) -100 min. max. max. description # parameter a1 data propagation delay, 4pt bypass, orp bypass 7.5 10.0 ns t pd2 a2 data propagation delay ns f max a3 clock frequency with internal feedback 135 100 mhz f max (ext.) ? clock frequency with external feedback mhz f max (tog.) ? clock frequency, max. toggle mhz t su1 ? glb reg. setup time before clock, 4 pt bypass ns t co1 a7 glb reg. clock to output delay, orp bypass ns t h1 ? glb reg. hold time after clock, 4 pt bypass 0.0 ns t su2 ? glb reg. setup time before clock 6.0 ns t co2 a1 0 glb reg. clock to output delay ns t h2 ? 1 glb reg. hold time after clock 0.0 ns t r1 a1 2 ext. reset pin to output delay, orp bypass ns t rw1 ? 3 ext. reset pulse duration 5.0 ns t ptoeen b1 4 input to output enable ns t ptoedis c1 5 input to output disable ns t goeen b1 6 global oe output enable ns t goedis c1 7 global oe output disable ns t wh ? 8 external synchronous clock pulse duration, high 3.5 ns t wl ? 9 external synchronous clock pulse duration, low 3.5 ns 100 143 5.0 4.0 5.0 9.0 12.0 12.0 7.0 7.0 10.0 77 100 6.5 0.0 8.0 0.0 6.5 5.0 5.0 13.0 5.0 6.0 12.5 15.0 15.0 9.0 9.0
specifications isplsi 2096ve 7 use isplsi 2096ve-250 for new designs internal timing parameters 1 over recommended operating conditions t io 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. 3. the xor adjacent path can only be used by hard macros. table 2-0036a/2096ve v.1.0 inputs units -250 min. max. description # 2 parameter 20 input buffer delay ns t din 21 dedicated input delay ns t grp 22 grp delay ns glb t 1ptxor 25 1 product term/xor path delay ns t 20ptxor 26 20 product term/xor path delay ns t xoradj 27 xor adjacent path delay ns t gbp 28 glb register bypass delay ns t gsu 29 glb register setup time before clock ns t gh 30 glb register hold time after clock ns t gco 31 glb register clock to output delay ns 3 t gro 32 glb register reset to output delay ns t ptre 33 glb product term reset to register delay ns t ptoe 34 glb product term output enable to i/o cell delay ns t ptck 35 glb product term clock delay ns orp t ob 38 output buffer delay ns t sl 39 output slew limited delay adder ns grp t 4ptbpc 23 4 product term bypass path delay (combinatorial) ns t 4ptbpr 24 4 product term bypass path delay (registered) ns t orp 36 orp delay ns t orpbp 37 orp bypass delay ns outputs t oen 40 i/o cell oe to output enabled ns t odis 41 i/o cell oe to output disabled ns t goe 42 global output enable ns t gy0 43 clock delay, y0 to global glb clock line (ref. clock) ns t gy1/2 44 clock delay, y1 or y2 to global glb clock line ns clocks t gr 45 global reset to glb 0.5 0.7 0.2 2.8 2.8 2.8 0.0 0.2 0.3 3.7 2.9 3.6 1.4 2.0 1.5 2.0 1.1 0.4 2.4 2.4 1.6 1.0 1.2 3.9 0.8 1.7 0.8 1.0 1.2 ?s global reset -200 min. max. 0.5 1.1 0.6 2.9 2.9 2.9 0.0 0.3 0.4 4.3 3.9 4.0 1.5 2.0 1.4 1.9 1.5 0.5 3.0 3.0 2.0 1.2 1.4 3.6 1.2 1.8 1.0 1.2 1.4
specifications isplsi 2096ve 8 internal timing parameters 1 over recommended operating conditions t io 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. 3. the xor adjacent path can only be used by hard macros. table 2-0036b/2096ve v.1.0 inputs units -135 min. -100 min. max. max. description # 2 parameter 20 input buffer delay ns t din 21 dedicated input delay ns t grp 22 grp delay ns glb t 1ptxor 25 1 product term/xor path delay ns t 20ptxor 26 20 product term/xor path delay ns t xoradj 27 xor adjacent path delay ns t gbp 28 glb register bypass delay ns t gsu 29 glb register setup time before clock ns t gh 30 glb register hold time after clock ns t gco 31 glb register clock to output delay ns 3 t gro 32 glb register reset to output delay ns t ptre 33 glb product term reset to register delay ns t ptoe 34 glb product term output enable to i/o cell delay ns t ptck 35 glb product term clock delay ns orp t ob 38 output buffer delay ns t sl 39 output slew limited delay adder ns grp t 4ptbpc 23 4 product term bypass path delay (combinatorial) ns t 4ptbpr 24 4 product term bypass path delay (registered) ns t orp 36 orp delay ns t orpbp 37 orp bypass delay ns outputs t oen 40 i/o cell oe to output enabled ns t odis 41 i/o cell oe to output disabled ns t goe 42 global output enable ns t gy0 43 clock delay, y0 to global glb clock line (ref. clock) ns t gy1/2 44 clock delay, y1 or y2 to global glb clock line ns clocks t gr 45 global reset to glb 0.5 1.7 1.2 4.7 4.7 4.7 0.5 0.3 1.1 6.1 6.9 5.0 1.6 2.0 3.7 3.7 1.5 0.5 3.4 3.4 3.6 1.6 1.8 5.8 1.2 3.8 1.6 1.6 1.8 0.7 2.5 1.8 6.2 6.2 6.2 1.0 0.3 3.1 7.1 9.1 5.6 1.6 2.0 5.2 4.7 1.7 0.7 3.4 3.4 5.6 2.4 2.6 7.1 1.7 4.8 2.6 2.4 2.6 ?s global reset
specifications isplsi 2096ve 9 isplsi 2096ve timing model glb reg delay i/o pin (output) orp delay feedback reg 4 pt bypass 20 pt xor delays control pts i/o pin (input) y0,1,2 grp glb reg bypass orp bypass dq rst re oe ck i/o delay i/o cell orp glb grp i/o cell #24 #25, 26, 27 #33, 34, 35 #43, 44 #36 reset ded. in #21 #20 #28 #29, 30, 31, 32 #38, 39 goe 0 #42 #40, 41 0491/2032 #22 comb 4 pt bypass #23 #37 #45 table 2-0042/2096ve derivations of t su, t h and t co from the product term clock = = = = t su 2.8ns logic + reg su - clock (min) ( t io + t grp + t 20ptxor) + ( t gsu) - ( t io + t grp + t ptck(min)) (#20 + #22 + #26) + (#29) - (#20 + #22 + #35) (0.5 + 0.2 + 2.8) + (0.8) - (0.5 + 0.2 + 0.8) = = = = t h clock (max) + reg h - logic ( t io + t grp + t ptck(max)) + ( t gh) - ( t io + t grp + t 20ptxor) (#20 + #22 + #35) + (#30) - (#20 + #22 + #26) (0.5 + 0.2 + 3.6) + (1.7) - (0.5 + 0.2 + 2.8) = = = = t co note: calculations are based upon timing specifications for the isplsi 2096ve-250l. clock (max) + reg co + output ( t io + t grp + t ptck(max)) + ( t gco) + ( t orp + t ob) (#20 + #22 + #35) + (#31) + (#36 + #38) (0.5 + 0.2 + 3.6) + (0.2) + (1.1 + 1.4) 2.5ns 7.0ns
specifications isplsi 2096ve 10 power consumption power consumption in the isplsi 2096ve device de- pends on two primary factors: the speed at which the device is operating and the number of product terms used. figure 3 shows the relationship between power and operating speed. figure 3. typical device power consumption vs fmax 0127/2096ve i cc can be estimated for the isplsi 2096ve using the following equation: i cc (ma) = 8.0 + (# of pts * 0.63) + (# of nets * fmax * 0.005) where: # of pts = number of product terms used in design # of nets = number of signals used in device max freq = highest clock frequency to the device (in mhz) the i cc estimate is based on typical conditions (v cc = 3.3v, room temperature) and an assumption of two glb loads on average exists. these values are for estimates only. since the value of i cc is sensitive to operating conditions and the program in the device, the actual i cc should be verified. notes: configuration of six 16-bit counters typical current at 3.3v, 25 c 140 120 180 050 100 150 200 250 f max (mhz) i cc (ma) isplsi 2096ve 200 220 240 260 160
specifications isplsi 2096ve 11 pin description input/output pins - these are the general purpose i/o pins used by the logic array. name table 2-0002-2096ve tqfp pin numbers description 21, 27, 35, 41, 51, 57, 64, 71, 85, 91, 99, 105, 115, 121, 128, 7, 19 48 77 14 15 112 20 22, 28, 36, 42, 52, 58, 65, 72, 86, 92, 100, 106, 116, 122, 1, 8, 80, 17 23, 29, 37, 43, 53, 59, 67, 73, 87, 93, 101, 107, 117, 123, 3, 9, i/o 0 - i/o 5 i/o 6 - i/o 11 i/o 12 - i/o 17 i/o 18 - i/o 23 i/o 24 - i/o 29 i/o 30 - i/o 35 i/o 36 - i/o 41 i/o 42 - i/o 47 i/o 48 - i/o 53 i/o 54 - i/o 59 i/o 60 - i/o 65 i/o 66 - i/o 71 i/o 72 - i/o 77 i/o 78 - i/o 83 i/o 84 - i/o 89 i/o 90 - i/o 95 24, 30, 38, 44, 54, 60, 68, 74, 88, 94, 102, 108, 118, 124, 4, 10, 25, 32, 39, 45, 55, 61, 69, 75, 89, 96, 103, 109, 119, 125, 5, 11, 26 33 40 46 56 62 70 76 90 97 104 110 120 126 6 12 18, 111, 34, 127 50, 63, 2, 95, 16, 114 31, 47, 66, 81, 79, 98, global output enables input pins. goe 0, goe 1 gnd v vcc cc ground (gnd) dedicated clock input. this clock input is connected to one of the clock inputs of all the glbs on the device. active low (0) reset pin which resets all of the registers in the device. reset y0, y1, y2 13, 49, 82 no connect. nc 1 tdi/in 0 bscan tms/in 1 113 84, 78 83, dedicated input pins to the device. in 4, in 5 tdo/in 2 tck/in 3 output/input ?this pin performs two functions. when bscan is logic low, it functions as an output pin to read serial shift register data. when bscan is high, it functions as a dedicated input pin. input ?dedicated in-system programming boundary scan enable input pin. this pin is brought low to enable the programming mode. the tms, tdi, tdo and tck controls become active. input ?this pin performs two functions. when bscan is logic low, it functions as a serial data input pin to load programming data into the device. when bscan is high, it functions as a dedicated input pin. input ?this pin performs two functions. when bscan is logic low, it functions as a mode control pin for the boundary scan state machine. when bscan is high, it functions as a dedicated input pin. input ?this pin performs two functions. when bscan is logic low, it functions as a clock pin for the boundary scan state machine. when bscan is high, it functions as a dedicated input pin. 1. nc pins are not to be connected to any active signal, vcc or gnd.
specifications isplsi 2096ve 12 pin configuration isplsi 2096ve 128-pin tqfp pinout diagram (0.4mm lead pitch/14.0 x 14.0mm body size) vcc i/o 85 i/o 86 i/o 87 i/o 88 i/o 89 i/o 90 i/o 91 i/o 92 i/o 93 i/o 94 i/o 95 1 nc y0 reset vcc goe 1 gnd bscan i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 vcc i/o 57 i/o 56 i/o 55 i/o 54 i/o 53 i/o 52 i/o 51 i/o 50 i/o 49 i/o 48 in 4 y1 nc 1 vcc goe 0 y2 tck/in 3 i/o 47 i/o 46 i/o 45 i/o 44 i/o 43 i/o 42 i/o 41 i/o 40 i/o 39 i/o 38 vcc i/o 84 gnd i/o 83 i/o 82 i/o 81 i/o 80 i/o 79 i/o 78 i/o 77 i/o 76 i/o 75 i/o 74 i/o 73 i/o 72 in 5 gnd i/o 71 i/o 70 i/o 69 i/o 68 i/o 67 i/o 66 i/o 65 i/o 64 i/o 63 i/o 62 i/o 61 i/o 60 gnd i/o 59 i/o 10 gnd i/o 12 i/o 13 i/o 14 i/o 15 i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 tms/in 1 1 nc gnd i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 i/o 32 i/o 33 i/o 34 i/o 35 gnd isplsi 2096ve top view vcc tdi/in 0 i/o 58 tdo/in 2 gnd i/o 37 i/o 11 vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 128 127 126 125 124 123 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 64 96 122 i/o 36 vcc 1. nc pins are not to be connected to any active signals, vcc or gnd. 0124-2096ve
specifications isplsi 2096ve 13 part number description isplsi 2096ve ordering information table 2-0041a/2096ve family f max (mhz) 200 135 ordering number package 128-pin tqfp t pd (ns) 4.5 7.5 isplsi isplsi 2096ve-200lt128* 250 128-pin tqfp 4.0 isplsi 2096ve-250lt128 *use isplsi 2096ve-250 for new designs 128-pin tqfp isplsi 2096ve-135lt128 100 128-pin tqfp 10 isplsi 2096ve-100lt128 commercial industrial table 2-0041b/2096ve family f max (mhz) 135 ordering number package 128-pin tqfp t pd (ns) 7.5 isplsi isplsi 2096ve-135lt128i device number isplsi 2096ve xx x xxxxx grade x speed 250 = 250 mhz f max 200 = 200 mhz f max* 135 = 135 mhz f max 100 = 100 mhz f max *use isplsi 2096ve-250 for new designs power l = low package device family 0212/2096ve t128 = 128-pin tqfp tn128 = lead-free 128-pin tqfp blank = commercial i = industrial conventional packaging lead-free packaging family f max (mhz) 135 ordering number package t pd (ns) 7.5 isplsi 250 lead-free 128-pin tqfp 4.0 isplsi 2096ve-250ltn128 lead-free 128-pin tqfp isplsi 2096ve-135ltn128 100 lead-free 128-pin tqfp 10 isplsi 2096ve-100ltn128 commercial industrial family f max (mhz) 135 ordering number package lead-free 128-pin tqfp t pd (ns) 7.5 isplsi isplsi 2096ve-135ltn128i

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